According to conventional prior art methods and structures when data packets are to be processed for transmission, if there is encountered a flow of data packets which is greater than the processor can handle, these data packets have been stored off the chip in DRAM memory devices in one or more queues. The DRAM storage devices techniques, while providing good storage space, nevertheless are rather slow, thus increasing latency, and during peak periods may not work effectively. Therefore, a more rapid access to enqueued data packets is desired to decrease latency and increase processing capabilities.